OBJECTIVE OF STOPWATCH WITH LAPTIMES

The objectives of this project:

#Build a fully functional stopwatch. 

THEORY OF PROJECT

The timer is really just a count down counter (i.e. it counts down to 0). When Reset is a “1” or if the counter value reaches 0, the counter gets reloaded with the preload value (supplied on the load number input port) and then begins counting back down to 0.

LINK BLOG DIAGRAM

ce is the clock enable. Tying this to ’1’ or Vcc, will cause the timer to run continuously. 

clk is the clock input. It is connected to the system MCLK signal. 

reset is the reset signal. It is an active high reset and is asynchronous to the clock input. load number is a 24-bit input bus which supplies a preload value (see below) for the timer. 

zero is the zero output signal which is asserted when the count reaches 0. The zero signal is only asserted for one clock period of clk. 

tp is a test point for the programmable timer. 

The output is a square wave at 1/2 the frequency of the zero output. 

counter is a 24-bit output bus which gives the state of the 24 bits of the counter. It is only used for debugging purposes. The zero output will be connected to the Incr input of the Mod4 state machine you design in part I of this project.

Sample Video from the youtube.com

https://www.youtube.com/watch?v=1XZArZLvEg0